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Digital Logic syllabus

ITM 1517 units · 45 topicsAcademic year 2083/84
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Digital Logic

7 units

1. Introduction (6 LHs)

  1. Digital versus analog signals
    1. Digital versus analog signals
  2. Digital integrated circuits (Advantage, Characteristics and Level of Integration)
    1. Digital integrated circuits (Advantage, Characteristics and Level of Integration)
  3. Digital system applications
    1. Digital system applications
  4. Digital codes and conversions
    1. Digital codes and conversions
  5. Decimal, binary, octal and hexadecimal codes
    1. Decimal, binary, octal and hexadecimal codes
    2. BCD code
    3. Excess-3 code
    4. Gray code
  6. Alphanumeric codes
    1. Alphanumeric codes: ASCII code and EBCDIC code
  7. Binary addition and subtraction
    1. Binary addition and subtraction
  8. 1’s complement and 2’s complement
    1. 1’s complement and 2’s complement
  9. Signed number representation
    1. Signed number representation.

2. Logic Gates (3 LHs)

  1. Basic gates, Derived gates and Universal gates (NAND, NOR) and their equivalents
    1. Basic gates, Derived gates and Universal gates (NAND, NOR) and their equivalents
  2. Realization of different gates using Universal gates
    1. Realization of different gates using Universal gates
  3. Applications of logic gates
    1. Applications of logic gates

3. Boolean Algebra and Logic Simplification (8 LHs)

  1. Boolean algebra and its laws
    1. Boolean algebra and its laws
    2. Demorgan’s Theorem
  2. Simplification of Boolean expressions
    1. Simplification of Boolean expressions
  3. Minterms and maxterms
    1. Minterms and maxterms
  4. Sum-of-product (SOP) and product-of-sum (POS) methods
    1. Sum-of-product (SOP) and product-of-sum (POS) methods
  5. Truth tables and Karnaugh map (Up to Four variables)
    1. Truth tables and Karnaugh map (Up to Four variables)
  6. Don’t care conditions
    1. Don’t care conditions
  7. Boolean Function simplification using Quine-McCluskey Method/Tabulation Method
    1. Boolean Function simplification using Quine-McCluskey Method/Tabulation Method.

4. Combinational Logic Circuits (12 LHs)

  1. Design procedures
    1. Design procedures
  2. Half-adder and full-adder design
    1. Half-adder and full-adder design
  3. Half-subtractor and full-subtractor design
    1. Half-subtractor and full-subtractor design
    2. Binary adder design
    3. BCD adder design
    4. Encoder designs
    5. Decoder designs
    6. Multiplexers design
  4. Boolean function implementation using multiplexer
    1. Boolean function implementation using multiplexer
  5. Demultiplexer design
    1. Demultiplexer design
  6. Seven-segment decoder
    1. Seven-segment decoder
  7. Magnitude comparators
    1. Magnitude comparators
    2. Code Converter
  8. Programmable Logic Devices (PLA and PAL design)
    1. Programmable Logic Devices (PLA and PAL design).

5. Sequential Logic Circuits (6 LHs)

  1. Latches and flip-flops
    1. Latches and flip-flops: SR, D, T and JK
  2. Characteristics Table
    1. Characteristics Table
  3. Excitation tables and characteristic equations of all flip flops
    1. Excitation tables and characteristic equations of all flip flops
  4. Master-slave flip-flops
    1. Master-slave flip-flops
  5. Flip-flop applications
    1. Flip-flop applications

6. Registers and Counters (10 LHs)

  1. Register
    1. Register
  2. Shift Register (SISO, SIPO, PISO, PIPO and Bidirectional Registers)
    1. Shift Register (SISO, SIPO, PISO, PIPO and Bidirectional Registers)
  3. Data transfer timing diagrams
    1. Data transfer timing diagrams
  4. Asynchronous counters (Up, Down, Mod-N and UP/Down asynchronous counters)
    1. Asynchronous counters (Up, Down, Mod-N and UP/Down asynchronous counters)
  5. Synchronous counters (Up, down, Mod-N, UP/Down synchronous counters)
    1. Synchronous counters (Up, down, Mod-N, UP/Down synchronous counters)
  6. Shift Register Counter
    1. Shift Register Counter
  7. Register and counter applications
    1. Register and counter applications.

7. Sequential Machine Designs (3 LHs)

  1. Sequential Machine design procedures
    1. Sequential Machine design procedures: state diagram (introduction and example only)
  2. Transition/ State tables
    1. Transition/ State tables
  3. Reduction of Redundant states
    1. Reduction of Redundant states
  4. Binary assignment tables
    1. binary assignment tables
  5. Excitation Table and output table
    1. Excitation Table and output table
  6. Derivation of flip-flop input and Circuit output function, design of a circuit diagram
    1. derivation of flip-flop input and Circuit output function, design of a circuit diagram.